Design of a Halftoning Integrated Circuit based on Analog Quadratic Minimization by Non-Linear Multistage Switched Capacitor Network

@inproceedings{bgrzd_iscas88,
    author  = "Bernard, T. and Garda, P. and Reichart, A. and Zavidovique, B. and Devos, F. ",
    title   = "Design of a Halftoning Integrated Circuit based on Analog Quadratic Minimization by Non-Linear Multistage Switched Capacitor Network",
  booktitle = "Proc. IEEE Int. Symp. on Circuits and Systems",
    address = "Helsinki, Finland",
    pages   = "1217-1220",
    month   = jun,
    year    = 1988
}

Abstract
In order to build a smart sensor, we are involved in the design of a monolithic array of cellular processors operating upon binary pictures. Dealing with continuous-tone scenes requires half-toning techniques, implementable in solid state circuit. In this paper, we present the design of a neural network performing the minimization of a quadratic distance between the analog acquired picture and a convolution of the resulting halftoned binary picture. We show that using a diffusion kernel and switched capacitor networks result in an effective halftoning circuit, well-suited to a very compact CMOS implementation. This design methodology can be fruitfully exploited for the implementation of a large class of early or low level vision problems, expressed as quadratic cost function minimization.

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