A 65x76 VLSI Retina for Rough Vision

@inproceedings{bndz_camp91,
    author  = "Bernard, T. and Nguyen, P. and Devos, F. and Zavidovique, B. ",
    title   = "A 65x76 {VLSI} Retina for Rough Vision",
  booktitle = "Proc. Workshop on Computer Architecture for Machine Perception",
    address = "Paris, France",
    pages   = "1-12",
    month   = dec,
    year    = 1991
}

Abstract
The VLSI Retina is a device which intimately associates an optoelectronic layer with processing facilities on a monolithic circuit. While providing a better balance between data flows and bandwidths, drawing together acquisition and processing is also expected to reveal friutful interaction opportunities between microelectronic phenomena and vision-oriented information processing. Compacity, versus versatility, leads to the use of a mesh array of bare boolean processors. This implies a memory shortage and limits the retina abilities to a rough type of vision, with which specific algorithmic techniques may cope. Using shift registers and tricky circuitry, a minimal retina circuit may be built with less than 30 transistors per pixel, and controled by as few as 5 clock signals. The successful integration, test and experimentation of a such 65x76 retina are presented.

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