Making the most of 15k lambda2 silicon area for a digital retina PE

@inproceedings{pmb_afpaec98,
    author  = "Paillet, F. and Mercier, D. and Bernard, T.M.",
    title   = "Making the most of 15k lambda2 silicon area for a digital retina {PE}",
  booktitle = "Proc. SPIE, Vol. 3410, Advanced Focal Plane Arrays and Electronic Cameras",
    editor  = "Bernard, T.M.",
    address = "Zürich, Switzerland",
    pages   = "?-?",
    month   = may,
    year    = 1998
}

Abstract
Lodging a digital processing element (PE) in each pixel of a focal plane array is the challenge to be taken up to get programmable artificial retinas (PAR) that can be used in a large variety of applications. Using semi-static memory and communication structures together with charge sharing based computing circuitry, we elaborate a PE architecture of which the computational power versus area ratio improves over all previously known attempts. A key feature is the ability of neighbor PEs to be gathered into clusters allowing to get virtual memory through multigranularity computation. A 128x128 PAR, called PVLSAR2.2, has been fabricated accordingly with 5 binary registers per PE. Each PE fits within a 15k lambda2 silicon area.

Paper (PostScript format compressed with gzip) -> paper.ps.gz (about 78K)

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